This invention relates to bistable logic circuits and more particularly relates to a novel bistable logic circuit normally testable without generating spurious activating outputs while installed and in service in a logic system.
A bistable logic circuit is often used for storing transitory signals in a logic system. The circuit inputs are characterized as being either the low, or logic zero, or the high, or logic 1, state of a bit of binary information. The memory function associated with the storage of this binary logic information is often realized by a dual-control bistable multivibrator, referred to as a flip-flop. The switching of the memory output from a logic zero state to a logic one state, and vice-versa, is caused by the application of special control signals to appropriate input terminals of the memory circuit. Various circuit configurations are known which utilize a variety of control signals to establish the desired output of the basic bistable operator. In all of these circuits the output is characterized as being switched from a logic zero to a logic 1 by the application of a set-output signal to the circuit Set input terminal and by being switched from a logic 1 to a logic zero by the application of a reset-output signal to the circuit Reset input. When both the Set and Reset inputs are simultaneously applied the circuit may be designed to prefer the Set input, so that the output is always set as a logic 1. The opposite preference, i.e., the output always being set as a logic zero, can also be designed for the simultaneous application of both input signals.
In some applications of the bistable memory circuit, a series of important control interventions is initiated by the switching of the memory output from a state of normal operation, which may, for example, be a logic zero, to a state of control intervention, i.e. a logic 1. The reliability of the control intervention depends on the integrity of the memory circuit. A faulty memory circuit which will not properly switch the output to a logic 1 and maintain that output after the Set signal has ceased, will prevent the proper occurance of the control intervention.
Because the control intervention of the memory circuit is required for the safety of the system, it is desirable to be able to test the memory circuit so as to insure the desired operating speed and integrity thereof. One method for accomplishing such integrity testing requires that the circuit be periodically removed from service while a test sequence is set up and executed by the system. This method results in a large percentage of total system time during which the system is removed from normal service. This system-out-of-service or "down" time is minimized by increasing the time period between the periodic tests while the probability of an undetected failure is allowed to increase. A second method for testing a bistable memory circuit is to add a Built In Test (BIT) sub-circuit to the logic system to periodically disconnect the memory circuit and perform an input-to-output signal flow test thereon. During a BIT sequence, a required control intervention will not be acted upon, since the bistable memory circuit is disconnected from the intervention signal generating device. The safety of the logic system is thereby jeopardized, so that the interval between BIT sequences is usually deliberately increased to reduce "down" time.